1. Field of the Invention
This invention relates to devices and methods for controlling data transfer such as DMA (Direct Memory Access) transfer using DMA controllers realizing reductions of interrupt processes with respect to central processing units (CPUs).
This application claims priority on Japanese Patent Application No. 2003-17681, the content of which is incorporated herein by reference.
2. Description of the Related Art
In general, systems having memories incorporate DMA (Direct Memory Access) controllers in order to reduce loads of CPUs (Central Processing Units), wherein peripheral modules for supporting functions of CPU communication devices and storage devices output DMA requests to DMA controllers so as to actualize data transfer based on the DMA system between source addresses and destination addresses, an example of which is disclosed in Japanese Patent Application Publication No. Hei 5-276221. In order to improve an efficiency in transferring data from a main memory of the system (or a system memory) having a great storage capacity to a peripheral module, the peripheral module must include a buffer memory (e.g., a first-in-first-out (FIFO) memory) having a small storage capacity for use in data transfer, whereby when transferring large-scale data stored in the main memory to the buffer memory of the peripheral module, the data are transferred in multiple divisions to suit the capacity of the buffer memory.
Next, a description will be given with respect to data-transfer procedures for transferring data of a system memory to a buffer memory incorporated in a peripheral module with reference to a flowchart shown in FIG. 5. Herein, the user of the system describes instructions regarding DMA requests in a program to be executed by a CPU in advance. During the process of executing the program, the CPU detects a DMA request that is described by the user in step S21. Upon detection of the DMA request, the CPU sets a certain number of times for transferring data per one DMA request into a transfer times register arranged in a DMA controller based on the stored content of the buffer memory incorporated in the peripheral module, which is a data-transfer destination, in step S22. In addition, the CPU stores the total number of times for transferring data in accordance with the amount of transferring data. Furthermore, the CPU sets a prescribed value representing a method how to designate addresses in transferring data to a DMA control register in step S23.
In step S24, a decision is made as to whether or not a DMA transfer is completed. When a decision result of step S24 is ‘NO’ (indicating that the DMA transfer is not completed), the flow proceeds to step S25 in which a decision is made as to whether or not the peripheral module provides a DMA request. The following steps S25–S27 are performed by the DMA controller. When a decision result of step S25 is ‘YES’ (representing that the peripheral module provides a DMA request), the flow proceeds to step S26 in which a DMA transfer is performed. After completion of a single DMA transfer, an interrupt signal is output to the CPU in step S27. Upon reception of such an interrupt signal, the CPU performs an interrupt process in accordance with an interrupt program. That is, the CPU performs an interrupt process at each time when receiving an interrupt signal. The foregoing step S24 designates an interrupt process as well. After completion of step S27, the flow returns to step S24. Thus, similar operations are repeatedly performed until the DMA transfer is completed with respect to all data of the main memory (or system memory) that should be subjected to transferring.
According to the conventionally-known data transfer described above, the CPU may frequently incur interrupts during the DMA transfer process. This raises a problem in that the CPU incurring numerous interrupts suffers from an excessively great overhead. Normally, a first-in-first-out memory (i.e., a buffer memory) for use in data transfer has a relatively small storage capacity that matches several tens of bytes, for example. This reduces the amount of data, which is subjected to DMA transfer in a certain period of time from the timing that the DMA controller receives a DMA request to the timing that the CPU is interrupted, to several tens of bytes at best. It may be generally known that an overhead of several micro-seconds or so occurs per single interrupt in a microcomputer in which an operating system (OS) is installed. As described above, the amount of data transferred per single DMA transfer must be limited to the storage capacity of the buffer memory, which is a transferring destination, or less. Therefore, as the storage capacity of the buffer memory is reduced, the CPU must frequently incur numerous interrupts.